Simulation Efficiency of Analog Behavioral Models- Analyses and Improvements (English shop)

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Abstract
In structured top-down design methodologies for the development of complex mixed-signal systems on chip, it is highly desirable to apply automated bottom-up modeling methods. These modeling methods are suited to generate behavioral models of analog blocks at the transistor level with the aim of speeding up simulations at higher abstraction levels. Without the application of behavioral models, verification at the system level is extremely costly in terms of computational effort for most modern designs – if not impossible.
Symbolic analysis offers promising approaches for automated, highly accurate, and flexible bottom-up modeling methods. These methods perform an automated model reduction that is applied to the circuit’s network equations and results in simplified but still complex differential algebraic equation systems. Based on these equations, behavioral models for different modeling languages can be generated. These models can subsequently be used to replace their corresponding transistor-level subsystem in order to enhance the simulation performance. Even though the applied model reduction algorithms are highly efficient, the resulting models’ performance is often unsatisfactory – sometimes even slower than at the transistor-level – making the application of such models impossible.
The objective of this work was to analyze and improve the simulation efficiency of such complex analytical models. This has been achieved by an adaptation of the behavioral models and the applied simulation algorithms, thus enhancing the simulation performance without loss of accuracy. The method is based on a highly efficient model compilation as well as on optimization strategies to reformulate the models’ DAEs with respect to the applied simulation algorithms. Thus, the simulation performance has been significantly improved by factors of up to two orders of magnitude. An important step towards efficient future use of symbolic methods for bottom-up model generation of analog circuits has been taken.