Zum Selbsttest von Verbindungsnetzen für Systems on Chip (English shop)

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The development of systems-on-chip — highly integrated circuits containing complete electronic systems on a single chip — is increasingly dominated by bus-based architectures. The reasons lie, on the one hand, in the reuse of subcircuits, so-called IP cores, which communicate with one another via buses, and, on the other hand, in the necessity of arranging interconnect systems hierarchically in order to reconcile a high interconnect density with short signal propagation delays on long inter-core lines.

Long, parallel-running lines such as buses are, with progressive feature-size scaling and higher clock rates, affected by disturbance effects due to line coupling, such as signal delay and crosstalk between adjacent lines. Inter-core buses will therefore constitute a bottleneck for the performance of core-based systems in the future. Nevertheless, no test method for inter-core buses has yet become established that adequately covers faults caused by line coupling.

This work first describes the realisation of a system-on-chip for the real-time encoding of high-resolution moving images. This system motivated the development of new tests for dynamic faults on inter-core buses and of self-test circuits for these buses.

The new interconnect tests are based on the well-known walking-1 test. They are extended in order to cover faults caused by capacitive and inductive line coupling. Shift-register-based self-test implementations are presented that can be integrated with minimal overhead into the new IEEE 1500 standard for testing embedded cores.

For a 16 bit bus system, a test circuit for interconnect self-test is presented that has been fabricated in a 0.25 μm technology. The effect of line coupling can be measured for this test circuit using an automatic test system for digital circuits. In the case of test signals with the most unfavourable line coupling, the test circuit achieves only about half the operating frequency compared with the case of the most favourable line coupling. This underlines the necessity of checking inter-core buses for coupling faults by means of a suitable test. The measurements show good agreement with simulations of an RLCM model of the bus system with a non-linear driver and load model.

Keywords: interconnect test, line coupling, self-test, systems-on-chip, IEEE 1500

Keywords: interconnect test, line coupling, system-on-chip