Entwurfsverfahren für asynchrone Schaltungen unter Verwendung von Standardsoftware (English shop)

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This work describes the systematic (semi-) automatic design of asynchronous circuits in a design environment for synchronous circuits. The methodology developed in this work allows to implement any behavioural model in stages of an asynchronous pipeline. Models can there­fore be described with standard hardware description languages (VHDL, Verilog, EDIF) and are allowed to have storing elements. As a result a gate netlist is obtained which timing behav­iour is validated by a pre-layout timing simulation. Controlling of each stage can be done with standardised or new defined control automata. DGC which can generate hazard free cir­cuits is used to synthesise the new defined control automata. Other synthesis steps and simula­tion are done with the common tool synopsys. Integrating the asynchronous moduls into an synchronous design is possible without problems. Further an extensive catalogue of control­lers for the four phase protocol was created. Additional interface modules are also part of the catalogue. These interface modules are for example connections to synchronous modules. The capacity of the software ASMOGEN as a part of this work is shown in a comparison between a synchronous implementation and an asynchronous one of a Reed Solomon decoder.