Performance of Time-Critical Embedded Systems under the Influence of Errors and Error Handling Protocols (English shop)

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Embedded systems in general, and safety-critical systems in particular, are becoming increasingly complex. In addition, the transient error rate is rising significantly due to the shrinking feature sizes of modern semiconductor processes. Therefore, error-free operation of future embedded, safety-critical systems under nominal conditions cannot be assumed.

As a rule of thumb, it can be said that the key parameters in the design space — performance, price and reliability — are almost always contradicting design goals. This work targets this design space, highlights the challenges and discusses the trade-offs.

Of particular interest is reliability under real-time aspects. Naturally, there are error-handling protocols, error-correcting codes and modular redundancy. However, the correction of errors always has a certain influence on the timing behaviour of the entire system. Even if an error could be corrected, it remains unclear under which situations the timing behaviour is met. This can lead to the absurd situation that an error in an advanced driver assistance system can be corrected, yet a missed deadline still causes a system failure.

In this work we present the ASTEROID platform, which was developed within a cooperation between TU Braunschweig and TU Dresden. This platform has been designed specifically with regard to real-time aspects, performance, reliability and, consequently, safety. ASTEROID differs from other MPSoC platforms in its cross-layer error-handling approach. The actual hardware platform implements only the absolute minimum of fault tolerance in order to support the operating system running on top of it.

The operating system then takes over the actual redundancy and thus allows a flexible mixture of redundant and non-redundant applications.

In this work, the platform is analysed with respect to real-time performance under errors in a compositional way. To this end, error effects in on-chip and off-chip communication as well as errors in the processing core itself are considered.

The scientific contribution of this work lies, on the one hand, in a generalised compositional performance analysis that additionally accounts for error effects. On the other hand, end-to-end protocols and redundant applications are modelled and analysed with respect to their real-time capability. For many of the employed methods, a reliability estimation of the timing behaviour under a given error model is also carried out.