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New Approaches to Reliability Qualification of Semiconductor Components under Varying and Progressive Stresses

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New Approaches to Reliability Qualification of Semiconductor Components under Varying and Progressive Stresses (English shop)

Alexander Hirler (Author)

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ISBN-13 (Hard Copy) 9783736975200
ISBN-13 (eBook) 9783736965201
Language English
Page Number 166
Lamination of Cover glossy
Edition 1.
Publication Place Göttingen
Place of Dissertation München
Publication Date 2021-11-15
General Categorization Dissertation
Departments Physics
Physics of condensed matter (including physics of solid bodies, optics)
Electrical engineering
Common electrical engineering
Keywords accelerated life test, acceleration model, AEC-Q100, alternating step-stress, alternating stress, applicability, application profile, application specific, Arrhenius model, automotive application, automotive electronics, automotive industry, autonomous driving, capacitor, collective mission profile, commutative stress, constant voltage stress, Cox's proportional hazard, cumulative damage, cumulative damage model, cumulative degradation, cumulative exposure, cumulative stress, cumulative stress modeling, cyclical stress test, driver assistance, effective stress, electric mobility, empirical verification, equivalent stress, experimental verification, exponential E model, extended lifetime, failure data, failure distribution, failure mechanism, functional load, interdependent stressors, lifetime extrapolation, lifetime measurement, load, lognormal distribution, mission profile, model verification, multi-dimensional, non-constant stress, operating condition, parameter extraction, Poisson scaling, power-law model, progressive stress, qualification plan, ramp, ramp voltage stress, ramp-stress, reliability, reliability capability, reliability evaluation, reliability extrapolation, reliability measurement, reliability methodology, reliability qualification, reliability theory, robustness validation, semiconductor component, semiconductor device, semiconductor reliability, SSALT, state-of-the-art semiconductor, step-stress, stress histogram, stress level, stress load, stress sequence, stress transformation, supply chain, tampered failure rate, tampered random variable, TDDB, technology assessment, Technology Black Box, temperature, test condition, test load, dielectric breakdown, time-dependent dielectric breakdown, transistor, varying stress, voltage, voltage ramp, Weibull, Weibull distribution, beschleunigter Lebensdauertest, Beschleunigungsmodell, AEC-Q100, Stufen-Wechselbeanspruchung, Wechselbeanspruchung, Anwendbarkeit, Anwendungsprofil, anwendungsspezifisch, Arrhenius-Modell, Automobilanwendung, Automobilelektronik, Automobilindustrie, autonomes Fahren, Kondensator, kollektives Einsatzprofil, kommutative Belastung, konstante Spannungsbelastung, Cox's proportionales Risiko, kumulativer Schaden, Schadensakkumulation, kumulative Degradation, kumulative Exposition, kumulative Belastung, Modellierung der kumulativen Belastung, zyklischer Stresstest, Fahrerassistenz, effektive Belastung, Elektromobilität, empirische Überprüfung, äquivalente Belastung, experimentelle Verifikation, Exponential-E-Modell, verlängerte Lebensdauer, Ausfalldaten, Ausfallverteilung, Ausfallmechanismus, funktionelle Belastung, voneinander abhängige Stressoren, Extrapolation der Lebensdauer, Lebensdauermessung, Belastung, Lognormalverteilung, Einsatzprofil, Modellüberprüfung, mehrdimensional, nicht-konstante Belastung, Betriebsbedingung, Parameterextraktion, Poissonskalierung, Potenzgesetz-Modell, progressive Belastung, Qualifizierungsplan, Rampe, Spannungsrampe, Rampenspannung, Zuverlässigkeit, Belastbarkeit, Zuverlässigkeitsbewertung, Extrapolation der Zuverlässigkeit, Zuverlässigkeitsmessung, Zuverlässigkeitsmethodik, Zuverlässigkeitsqualifikation, Zuverlässigkeitstheorie, Robustheitsvalidierung, Halbleiterbauelement, Halbleiterzuverlässigkeit, SSALT, State-of-the-art Halbleiter, Stufenstress, Stresshistogramm, Stresslevel, Stressbelastung, Stresssequenz, Stresstransformation, Lieferkette, manipulierte Ausfallrate, manipulierte Zufallsvariable, TDDB, Technologiebewertung, Technologie-Black-Box, Temperatur, Prüfbedingung, Prüflast, dielektrischer Durchbruch, zeitabhängiger dielektrischer Durchbruch, Transistor, wechselnde Belastung, Spannung, Spannungsrampe, Weibull, Weibull Verteilung
URL to External Homepage https://www.unibw.de/physik
Description

In the present work, urgent issues in the reliability qualification of semiconductor devices are addressed, which particularly affect value chains such as those in the automotive industry. These have particularly high requirements for long lifetime and low failure rates of their products, which are additionally exposed to more extreme operating and environmental conditions than in most other areas of application. In particular, the question arises on how to assess a product or semiconductor technology against the requirement of an application-specific mission profile with multiple non-constant stressors.

For this purpose, the behavior of failure distributions under varying and progressive stress loads is investigated and described using cumulative damage models. For the first time, the industry-wide approach of transforming non-constant mission profiles into effective constant stress and test conditions for reliability assessment and qualification can be physically justified and substantiated with measurement data. This stress transformation is exemplified using the time-dependent dielectric breakdown (TDDB) failure mechanism with the two stressors voltage and temperature; and then extended to include the use of multi-dimensional mission profiles and interdependent stressors. These measurements are performed on university metal–oxide–semiconductor (MOS) capacitors as well as on commercially available state-of-the-art transistors. Finally, it is demonstrated that the obtained findings in the field of cumulative damage can be applied to use reliability studies with ramp-stress for acceleration model verification and to determine model parameters with less time and experimental effort.